1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Background Art
Heretofore, a package type semiconductor device wherein a semiconductor element (a semiconductor chip) is mounted on an island portion on a lead frame, and an electrode pad on the semiconductor element and a lead portion on the lead frame are wire bonded (connected) together, is publicly known. A plurality of unit cells (functional units of the element) configuring the semiconductor element are electrically connected to the electrode pad, and current flowing through the unit cells is extracted to the outside via the bonding wires and lead portion. In order to cause the current to flow uniformly through the unit cells, the plurality of unit cells are disposed in equal proportions from the electrode pad and wire bonding positions toward the outer side of the semiconductor element. A description will be given of a planar layout of a heretofore known semiconductor device.
FIGS. 16A, 16B, and 16C are plan views showing examples of a planar layout of the heretofore known semiconductor device. FIGS. 16A to 16C show examples of a case wherein wire bonding is performed on the front surface of a semiconductor element (semiconductor chip) 101, in equal proportions in the surface area of the semiconductor element 101 (hereafter described simply as in equal proportions), so that current flows uniformly through unit cells (hereafter referred to as heretofore known examples 1 to 3). The heretofore known examples shown in FIGS. 16A, 16B, and 16C are a package type semiconductor device wherein the semiconductor element 101 is fixed (mounted) to, and a rear surface electrode is connected to, an island portion 100a on a lead frame 100. A plurality of unit cells (not shown) are disposed in an active region (the portion bounded by the rectangular frame indicated by the dashed line) 102 of the semiconductor element 101. The active region 102 is a region through which current flows when in on-state.
Also, in the active region 102, for example, an electrode pad 103 having a substantially rectangular plan-view shape with substantially the same dimensions as those of the active region 102 is disposed on the semiconductor element 101. A plurality of wires 104 are wire bonded (connected) to the electrode pad 103 so as to be positioned in equal proportions in the surface area of the electrode pad 103 (hereafter described simply as positioned in equally proportions). Each wire 104 extracts current from a plurality of unit cells disposed within a predetermined region with the junction with the electrode pad 103 as a center. That is, when it is supposed that the active region 102 is divided equally into a plurality of segments, each of the junctions of the wires 104 and electrode pad 103 is positioned in substantially the center of a portion of the electrode pad 103 positioned in a corresponding segment of the active region 102. Each wire 104 takes charge of the current in a corresponding one of the segments of the active region 102.
Specifically, the heretofore known example 1 shown in FIG. 16A is an example wherein the active region 102 is divided into four rectangular segments 102a to 102d of substantially the same dimensions (divided into quarters) by two straight lines which are parallel to respective two sides sharing one vertex and perpendicular to each other passing through the center of the rectangle. Two wires 104 are joined to the electrode pad 103. The junctions of the wires 104 and electrode pad 103 are positioned one in substantially the center of a portion of the electrode pad 103 positioned in each segment 102a to 102d of the active region 102. The two wires 104 are each joined to two portions of the electrode pad 103 (for example, one wire 104 is joined to portions corresponding to the segments 102a and 102b, and the other wire 104 is joined to portions corresponding to the segments 102c and 102d).
The heretofore known example 2 shown in FIG. 16B is an example wherein the active region 102 is divided into three stripe segments 102e to 102g of substantially the same width (divided equally into thirds) by two straight lines parallel to one side. Three wires 104 are joined to the electrode pad 103. The junctions of the wires 104 and electrode pad 103 are positioned one in substantially the center of a portion of the electrode pad 103 positioned in each segment 102e to 102g of the active region 102. In the heretofore known example 3 shown in FIG. 16C, four wires 104 are joined to the electrode pad 103. The positions of the junctions of the wires 104 and electrode pad 103 are the same as in the heretofore known example 1. Different wires 104 are joined one to each junction with the electrode pad 103.
The portion of each wire depicted in the curved line is a portion which is looped so as to make no contact with the peripheral portion of the semiconductor element 101, and the portion of each wire depicted on the electrode pad 103 in the short vertical line is a junction with the electrode pad 103 (the same applies to FIGS. 17A to 17C). In each heretofore known example 1 to 3, the wires 104 are connected to the lead portion 100b on the lead frame 100, thus electrically connecting the lead portion 100b and the electrode pad 103. The wires 104 have a function to extract to the outside the current flowing through the unit cells disposed in the active region 102. For example, a control electrode pad 105 is disposed in the vicinity of the outer periphery of the active region 102. The control electrode pad 105 is connected to another lead portion 100c on the lead frame 100 by a wire 106.
Also, the semiconductor device is required to respond to a larger current as well as to be more highly functionalized, and sensing or control by an integrated circuit (IC) is being carried out. As the IC which carries out sensing or control is disposed on the semiconductor device, a restriction occurs in electrode pad layout, wire bonding position, or the like. Consequently, it is difficult to equalize the balance of the electrode pad layout, and of the wire bonding positions, on the semiconductor element so that current flows uniformly through the unit cells, and a bias occurs in the size of current flowing through a front surface electrode (an electrode common to the unit cells) of the semiconductor element. In recent years, the channel resistance of unit cells decreases owing to an advancement in microfabrication technology or the like, thus making it easy for the current to flow. Therefore, there is the problem that an increase in the current capacity per unit area leads to a substantial increase in the current density in a portion in which the current concentrates, thus resulting in a decrease in short-circuit resistance.
FIGS. 17A to 17C show examples of a case wherein a bias occurs in the size of the current flowing through the front surface electrode of the semiconductor element 101, due to the fact that the wire bonding positions on the semiconductor element 101 are not in equal proportions in the surface area of the electrode pad 103 (hereafter described simply as not in equal proportions) (hereafter referred to as heretofore known examples 4 to 6). FIG. 17A to 17C are plan views showing other examples of the planar layout of the heretofore known semiconductor device. The heretofore known example 4 shown in FIG. 17A is different from the heretofore known example 3 (refer to FIG. 16C) in that an IC 107, apart from the electrode pad 103, is disposed on the semiconductor element 101. In the heretofore known example 4, a plurality of electrode pads 103 smaller in surface area than in the heretofore known example 3 are disposed in parallel, on the semiconductor element 101, in the vicinity of, and along the outer periphery of, the active region (not shown). An electrode of unit cells (not shown) is provided substantially all over the active region, and the electrode pads 103 are joined to the electrode.
In the heretofore known example 4, as a mask (an IC 107) occupies a large portion on the semiconductor element 101, a region on the semiconductor element 101 in which the electrode pads 103 can be disposed is narrowly limited, and the electrode pads 103 are disposed leaning closer to the outer peripheral side than the central portion of the semiconductor element 101. That is, the plurality of electrode pads 103 cannot be disposed in equal proportions on the semiconductor element 101. Therefore, the junctions of the wires 104 and electrode pads 103 are also not positioned in equal proportions on the semiconductor element 101, and the wire bonding positions lean closer to the outer peripheral side than the central portion of the semiconductor element 101. Consequently, unit cells disposed (on the side of semiconductor portions) immediately below the IC 107 are a long distance from the junctions of the wires 104 and electrode pads 103 compared with unit cells disposed in portions other than immediately below the IC 107.
The heretofore known examples 5 and 6 shown in FIGS. 17B and 17C are different from the heretofore known example 2 (refer to FIG. 16B) in that the positions of the junctions of the wires 104 and electrode pad 103 lean to one side of the electrode pad 103. In the heretofore known example 5, the positions of the junctions of the wires 104 and electrode pad 103 lean to the opposite side (the right side in the drawing) from the side facing the control electrode pad 105. Therefore, the segment 102e, of the segments 102e to 102g of the active region 102, closest to the control electrode pad 105 side (the left side in the drawing) is large in size and in the number of unit cells compared with the other segments 102f and 102g. That is, the unit cells of the segment 102e closest to the control electrode pad 105 side are a long distance from the junctions of the wires 104 and electrode pad 103 compared with the unit cells of the other segments 102f and 102g. 
In the heretofore known example 6, the widths of the segments 102e to 102g of the active region 102 are all substantially equal to each other in the same way as in the heretofore known example 2, but the positions of the junctions of the wires 104 and electrode pad 103 lean to the lead portion 100b side (the lower side in the drawing). Therefore, all the segments 102e to 102g of the active region 102 are large in the number of unit cells on the side (the upper side in the drawing) farther apart from the lead portion 100b than the wires 104 compared with on the side closer to the lead portion 100b than the wires 104. That is, the unit cells on the side farther apart from the lead portion 100b than the wires 104 are a long distance from the junctions of the wires 104 and electrode pad 103 compared with the unit cells on the side closer to the lead portion 100b side than the wires 104. This kind of one-sided leaning of the positions of the wire bonding positions in the heretofore known examples 5 and 6 results from, for example, an attempt to improve workability or various factors when assembling.
When the electrode pad layout on and the wire bonding positions on the semiconductor element 101 are not in equal proportions in this way, current flowing from the unit cells toward the wires 104 becomes partially larger, and a bias occurs in the size of current flowing through the front surface electrode of the semiconductor element 101. The reason is as follows. FIG. 18 is an illustration schematically showing a condition wherein a bias is occurring in the size of the current flowing through the front surface electrode of the semiconductor element. FIGS. 19A and 19B are illustrations showing a structure of unit cells in FIG. 18. Herein, as a unit cell, a metal oxide semiconductor field effect transistor (MOSFET) of a trench gate structure is shown by example. In an example wherein a source electrode (a front surface electrode) 120 doubling as the electrode pad 103 is provided substantially all over the active region 102 as in, for example, the heretofore known examples 5 and 6, a condition in the vicinity of one wire 104 joined to the source electrode 120 is shown in FIG. 18.
Also, in FIG. 18, flows of current, which passes through the source electrode 120 and is extracted from the wire 104 to the outside, are shown in order by the arrows identified by signs 121 to 124. The size of the arrows represents the size of the current. FIG. 19A shows a planar structure of semiconductor portions of unit cells, and FIG. 19B shows a sectional structure along the section line AA-AA′ of FIG. 19A. In each unit cell, the current 121 flows from the drain side to the source side through an n-type inversion layer (a channel) formed in a portion of a p−-type base region 112 along either trench 115, as shown in FIGS. 18, 19A, and 19B. As the current 121 passing through the channels of the unit cells reaches the source electrode 120, passes through the source electrode 120, and is extracted from the wire 104 to the outside, the current 121 collects at the junction 104a of the wire 104 and source electrode 120.
Specifically, as all the unit cells are of the same configuration, the current 121 flows uniformly throughout the semiconductor portions of the semiconductor element 101. Also, in a region (hereafter referred to as a mesa portion) sandwiched between adjacent trenches 115 disposed in a planar layout of stripes, unit cells are disposed in series in a direction in which the trenches extend in stripes. In each mesa portion, as an n+-type source region 113 is provided continuously, in the direction in which the trenches 115 extend in stripes, in the inner portion of a p−-type base region 112, the channel is formed all over the mesa portion. Therefore, the current 121 passing through the channels of the unit cells reaches the source electrode 120 lower in resistance than the semiconductor portions (mesa portions), from all over the mesa portions, without being suppressed. When the semiconductor element 101 is microfabricated, the number of unit cells disposed in the semiconductor element 101 increases, meaning that the current 121 reaching the source electrode 120 from the unit cells increases.
The current 122 having reached the source electrode 120 flows through the source electrode 120 toward the wire 104. At this time, as the current 123 flowing through the source electrode 120 heads toward the wire 104 while collecting the current 122 having reached the source electrode 120 from other unit cells disposed immediately below current paths, the closer to the wire 104, the larger the current 123. Also, the longer the distance from unit cells disposed on the outermost side (in the vicinity of the outer periphery of the active region 102) to the junction 104a of the wire 104 and source electrode 120, that is, the longer the current paths of the current 123 flowing through the source electrode 120, the larger the number of other unit cells disposed immediately below the current paths. Therefore, the longer the current paths, the more of the current 122, which has reached the source electrode 120 from the other unit cells, the current 123 flowing through the source electrode 120 collects, and the larger the current 123 becomes.
That is, in the heretofore known example 4, the current flowing from the IC 107 side toward the wires 104 is larger than the current flowing from the other portions toward the wires 104. In the heretofore known example 5, the current flowing from the segment 102e closest to the control electrode pad 105 side (the left side in the drawing) toward the wires 104 is larger than the current flowing from the other segments 102f and 102g toward the wires 104. In the heretofore known example 6, the current flowing from the portion (the upper side in the drawing) farther apart from the lead portion 100b than the wires 104 toward the wires 104 is larger than the current flowing from the side closer to the lead portion 100b than the wires 104 toward the wires 104. In this way, in the heretofore known examples 4 to 6, the current concentrates in the vicinity of one portion of the junctions of the wires 104, thus leading to a decrease in short-circuit resistance. In FIG. 18, signs 111, 114, and 116 to 119 are an n−-type drift layer, a p+-type contact region, a gate insulating film, a gate electrode, and an oxide film, and an interlayer insulating film respectively.
As a configuration which suppresses a decrease in short-circuit resistance due to the current concentration, the following three configurations are common. FIG. 20 is a circuit diagram showing a circuit configuration of a heretofore known semiconductor device. The first configuration is a configuration wherein the current concentration is suppressed by preventing a bias from occurring in the size of the current flowing through the front surface electrode of a semiconductor element 130, by connecting a ballast resistor 132 to the drain of each unit cell 131, as shown in FIG. 20. A configuration wherein a ballast resistor is provided in the inner portion (in the inner portion of the n−-type drift layer) of the semiconductor element is proposed (for example, refer to JP-A-5-063185). The second configuration is a configuration wherein the current density in a portion in which current concentrates is reduced by increasing the size (chip size) of the semiconductor element. The third configuration is a configuration wherein the current concentration is suppressed by using unit cells (low in conduction ability) through which it is difficult for the current to flow.
As a device using unit cells low in conduction ability, a device wherein the conduction ability of a cell structure positioned immediately below the junction of an emitter wire is made lower than the conduction ability of another cell structure positioned in a portion other than immediately below the junction of the emitter wire, is proposed (for example, refer to JP-A-2010-00040003 (Paragraphs 0060 and 0061)). Also, as another device, a device wherein the current density in a region close to a bonding pad portion is made lower than the current density in a region apart from the bonding pad portion, is proposed (for example, refer to JP-A-5-063202 (Paragraph 0008)). In JP-A-2010-004003 and JP-A-5-063202, unit cells low in conduction ability are disposed immediately below the junction of the wire wherein the current density is high, thereby reducing the current density, thus relaxing the current concentration immediately below the junction of the wire.
As a device with the conduction ability adjusted, a device including a cell wherein an n+-type source region and a p-type base region are in direct contact with an emitter electrode, and a cell wherein the n+-type source region and p-type base region are in no direct contact with the emitter electrode by being covered with an interlayer insulating film, is proposed (for example, refer to JP-A-2001-308327 (Paragraphs 0016 and 0017, FIG. 1)). In JP-A-2001-308327, the ratio of the cells wherein the n+-type source region and p-type base region are in no direct contact with the emitter electrode is optimized, thus reducing an on-voltage using an injection enhanced (IE) effect, and preventing the current density in channels from decreasing.
Also, as another device, a device wherein in an insulated gate bipolar transistor (IGBT) of a trench gage structure, trenches disposed in a planar layout of stripes, and p-type base regions disposed in a planar layout of stripes, are provided so as to be perpendicular to each other, is proposed (for example, refer to JP-A-2000-228519 (Paragraph 0049, FIG. 6)). In JP-A-2000-228519, unit cells are disposed at predetermined intervals in a direction in which the trenches extend in stripes, and the area occupied by the unit cells is reduced, thereby reducing conduction ability.
Also, as another device, a device wherein a dummy cell configured of only a p+-type contact region is provided, so as not to face an IGBT unit cell with a trench sandwiched in between, between IGBT unit cells which are adjacent to each other in a direction in which trenches extend in stripes, between adjacent trenches disposed in a planar layout of stripes, is proposed (for example, refer to JP-A-2007-221012 (Paragraphs 0029 and 0030, FIGS. 1 and 2)). In JP-A-2007-221012, dummy cells, which do not function as IGBTs by providing no n+-type emitter region, are selectively disposed, thereby preventing current from being unable to be interrupted when carriers concentrate.
Also, as another device, a device wherein two stripe n+-type source regions provided along each trench are cut into non-continuous shapes, between adjacent trenches disposed in a planar layout of stripes, so that the n+-type source regions are intermittent at regular intervals and that the n+-type source regions of one stripe alternates with the n+-type source regions of the other, is proposed (for example, refer to JP-A-2009-289988 (Paragraphs 0012 and 0015, FIGS. 1 and 2) and JP-A-2004-111772 (paragraph 0039, FIG. 2)). In JP-A-2009-289988, n+-type source regions of a planar pattern shape in no contact with the whole of the sidewall of each trench are provided, thereby reducing the effective current density in channels so as to suppress a rise in on-resistance and an increase in feedback capacity.
However, in the first to third configurations, it is possible to suppress a decrease in short-circuit resistance due to the current concentration, but a new problem arises. Specifically, in the first and third configurations, the current density in the channels of the unit cells decreases, due to which the on-resistance of the whole of the semiconductor element increases, thus resulting in an increase in conduction loss. In the second configuration, the size (chip size) of the semiconductor element increases, due to which cost increases, and gate capacity increases, thus resulting in an increase in switching loss.